the advent of the Multimedia Age, the system requirements of programs
dramatically. The complexities of
these applications require that processors be powerful, yet flexible enough to accommodate
various classes of applications efficiently. Recently, various reconfigurable
processors have been considered for satisfying these requirements. Reconfigurable
computing represents a median between general purpose processors, which are capable of
running different applications at the cost of increased execution time, as well as for
Application-Specific Integrated Circuits (ASICs), which are processors only suitable for
running certain types of applications but with much faster implementations. The
software programmer or the compiler of a reconfigurable processor should
be capable of recognizing the configuration that is best suited for the
program (or portion of) in
question and ensuring that the processor is set to that configuration.
Traditional reconfigurable processors are statically reconfigurable,
which means that the processor is configured at the start of program
execution and remains unchanged for the
duration of the program. In order to reconfigure a statically reconfigurable
processor, program execution would have to be halted while the reconfiguration is in
progress, slowing down the execution of the program. Dynamically
reconfigurable processors, on the other hand, allow reconfiguration and
execution to proceed at the same
The MorphoSys project proposes to design a unique dynamically reconfigurable
computer architecture geared toward increasing performance of image processing
applications. The main components of the architecture (Figures
1 and 2) are the Tiny Reduced Instruction Set Computer (RISC) processor,
Reconfigurable Cell (RC) Array, Context Memory, Frame
Buffer (FB), Direct Memory Access (DMA) Controller, and main memory (i.e.
DRAM, SRAM or RAMBUS).
The MorphoSys top-level block diagram
MorphoSys system interface
other components (not shown) complete the architecture: secondary
hard drive) and the external interface of the architecture (i.e.
to the input and output ports). Tiny RISC is a general purpose
processor that handles all instructions not related specifically
to image processing. The RC Array is the dynamically reconfigurable
co-processor that handles most of the image processing for MorphoSys. The
Context Memory stores configurations (called contexts) for the
RC Array; the FB and DMA Controller act as the interface between
the RC Array and the other components of MorphoSys.
At the time of this writing, the Tiny RISC processor, DMA Controller,
and FB have been modeled in behavioral VHDL code; the VLSI design
stage of these components
has begun. The VLSI design of the RC Array is complete.
Instruction set of the
The current MorphoSys
instruction set consists of 44 Tiny RISC instructions (including
newly-added Branch If Greater Than, Branch If Less Than, and Branch
If Equal To) and 12 instructions for the operation of the RC Array,
FB and DMA Controller.
of the MorphoSys Architecture
The FB is a fast memory buffer used to store portions of frames of data (in
image processing applications, each image is called a frame). It is the
buffer between the DMA Controller and RC Array. The DMA Controller has
a 64-bit data bus connection to the FB. The same bus is used for
reading and writing data to and from the FB, and therefore the DMA Controller
may not read and write at same time. The RC Array has two 64-bit