Lanes, RCs in adjacent quadrants can send data (denoted by E for Express) to each other without having to go through other RCs, thus saving time. While quadrants which are diagonally across from each other need to use an intermediate quadrant to transfer data between them, it has been determined that this does not occur often in the applications of interest.   Hence the resulting performance degradation should not be significant. Figure 5 shows the two ports of an RC: Port A has the inputs IA (Immediate value for Port A, from Frame Buffer), LA (Left, Port A), M (Middle), R (Right), T (Top), C (Center), B (Bottom), XQ (Cross-quadrant), FB (Feedback), and R0 to R3 (data from the 4-deep Register File of the RC); Port B has the inputs IB (Immediate value for Port B, from FB), U (Up), D (Down), LB (Left, Port B), and R0 to R3 (data from the 4-deep Register File of the RC).  XQ is data that comes from the cell in the next quadrant directly across from the RC in question.   The Feedback input to Port A is the input selected for Port A in the previous cycle.  The Register File holds up to four previous outputs of the RC (R0 to R3) and can supply them as inputs to the RC.  Note that IA and IB are different data (coming on two separate buses from the FB).

Figure14.GIF (9043 bytes)
Figure 14
Tiny RISC pipeline stages 1 and 2

Tiny RISC processor:
Tiny RISC is a 4-stage pipelined processor (Figures 14 and 15), designed at the University of California, Irvine by Christopher Christensen as a powerful 16-bit RISC microprocessor.  For the MorphoSys project, the design was modeled in behavioral VHDL and the data and address bus sizes were increased to 32 bits.  Tiny RISC has four important registers in addition to the Register File and the Special Register File.   The first is the Program Counter register, which contains the address of the program execution point.  The other three are pipeline registers, which provide the latched interface between each pipeline stage.  All processor registers, except the first pipeline register, are synchronous to the

rising edge of the global clock.  The first pipeline register is latched when the instruction acknowledge signal is lowered by the instruction cache controller (which indicates that the instruction is ready).

Figure15.GIF (8609 bytes)
Figure 15
Tiny RISC pipeline stages 3 and 4

The first stage is the Instruction-Fetch stage, where the 32-bit instruction is fetched from the instruction cache.  The next stage, the Instruction-Decode stage, includes the Register File and the Special Register File.  The Register File consists of sixteen 32-bit registers designed to hold regular data, while the Special Register File has five 32-bit registers designed to hold certain important information relating to interrupts and interrupt returns.  Table 1 describes the purpose of each Special Register.  The Execution stage is the third pipeline stage, and consists of the Arithmetic Logic Unit (ALU) and the interface to and from the data memory. The Execution stage also includes the Branch Unit, which contains all the logic necessary for determining the next PC value (which is normally incremented, unless the instruction requires a Jump). The final stage is the Writeback stage, where the output from the ALU or the data requested from memory is written back to the Register File. If the instruction is MTS (Move To Special Register), the data stored in the Register File location specified is written back to the Special Register specified.  If the instruction is MFS (Move From Special Register), the opposite is done.

Due to its pipelined architecture, Tiny RISC requires two forwarding units to avoid costly delays due to Read After Write (RAW) dependencies.  This occurs because it takes the processor two cycles after an instruction has been decoded to write data back to the Decode stage.  The two instructions immediately following the instruction in question will need to obtain the updated data (if they are reading from the register that is being written back to). One forwarding unit appears in the

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